(a) Use the setup, hold, and propagation delay times from a data manual to determine if the SN74109 J-K flip-flop in the circuit shown in the following figure will toggle. Also, plot the waveform of Q. (Assume that the flip-flop is initially Reset, the clock period is sufficiently long, and remember that for a toggle J = 1 and K = 0.)So7410910 1520 Delay (ns)Clock101520(b) How is it if the J-K flip flop is replaced by a 74LS112 and the delay time is reduced to 10ns, as shown in the following fig
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