News

EDN15y

EDN Access–04.10.97 VHDL and Verilog fundamentals–expressions, operands, and operators

The data objects in VHDL and Verilog form expression operands. Knowing the operand differences between the two HDLs helps you write more efficient chip-design code. Expressions consist of operators ...
EDN15y

The VHDL and Verilog story

I put a blog entry up on the Oasys blog about their new release, which is the first to support VHDL. But a couple of people told me it was a nice recounting of history so I decided to put a more ...
Electronic Design24y

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Design-Reuse10y

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
Electronics Weekly22y

VHDL/Verilog training comes with free development board

Esperan is running its project-based HDL training courses through June and July. The aim, says the training company, is to allow designers to implement their project in hardware using supplied ...
Ars Technica12y

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
Ars Technica20y

TCL/TK and VHDL/Verilog simulators

I got the 4th edition of Practical Programming in Tcl and Tk. So I got Tcl 8.4 installed and I'm ready to start with the book. But it's quite a tome. I was wondering if anyone had any advice when it ...