Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
EDN

High-Speed Quad 2-Input NAND Gate

The 74AHC00-Q100; 74AHCT00-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. JESD7-A. The ...
TechRepublic

Low Power With Improved Noise Margin for Domino CMOS NAND Gate

With the advancement in semiconductor technology, chip density and operating frequency are increasing, so the power consumption in VLSI circuits has become a major problem of consideration. More power ...
Digi Times

Kioxia, YMTC jump ahead with wafer-bonded NAND in volume production

Kioxia and YMTC are pioneering the use of wafer bonding technologies— CMOS directly Bonded to Array (CBA) and Xtacking, respectively — for next-generation NAND flash memory production. This strategic ...
techtimes

Samsung 900-Layer NAND Prototype Sets World Record: CMB Technique Doubles Stack Height

Samsung Electronics has produced the world's first functioning 900-layer V-NAND flash memory prototype — a record that nearly triples the layer count of any chip currently in mass production and ...